Development Board for Programmable Logic Devices using the MAX II EPM240 Altera CPLD Chip. Ideal for protyping dedicated controllers etc.
The CPLD (Complex Programmable Logic Array) has the following features:
Instant-on, non-volatile architecture
Reprogrammable: Yes
MicroCells: 192
Logic Array Blocks: 24
Logic Elements: 240 (10/LAB)
I/O Lines: 80 Programmable Bi-directional
I/O Levels: 1.5 to 3.3V supported
I/Os are fully compliant with the Peripheral Component
Interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2 for 3.3-V
Memory: 8K user
Clock: 50.000MHz onboard Osc.
Supply V: 5VDC (Onboard 3.3V Regulator)
I: <60mA (Use dependent)
10 Pin JTAG test header
Alternate Action Power Switch
5.5/2.1mm Coaxial Power Jack NOTE: This is a logic arrray that requires you to configure the internal logic and I/O to your needed configuration.
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Programmable using Byte Blaster, USB Blaster & Others. L: 2-3/4” W: 2” H: 3/4” WT: .06
